Freescale Semiconductor DSP56366 - Manual (Page 186)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
8-36 Freescale Semiconductor
a word is received, it indicates (only in the network mode) that the frame sync did not occur during
reception of that word. RFS is cleared by hardware, software, ESAI individual, or STOP reset. RFS is valid
only if at least one of the receivers is enabled (REx=1).
NOTE
In normal mode, RFS always reads as a one when reading data because there
is only one time slot per frame – the “frame sync” time slot.
8.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7
The ROE flag is set when the serial receive shift register of an enabled receiver is full and ready to transfer
to its receiver data register (RXx) and the register is already full (RDF=1). If REIE is set, an ESAI receive
data with exception (overrun error) interrupt request is issued when ROE is set. Hardware, software, ESAI
individual, and STOP reset clear ROE. ROE is also cleared by reading the SAISR with ROE set, followed
by reading all the enabled receive data registers.
8.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8
RDF is set when the contents of the receive shift register of an enabled receiver is transferred to the
respective receive data register. RDF is cleared when the DSP reads the receive data register of all enabled
receivers or cleared by hardware, software, ESAI individual, or STOP reset. If RIE is set, an ESAI receive
data interrupt request is issued when RDF is set.
8.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9
When set, REDF indicates that the received data in the receive data registers of the enabled receivers have
arrived during an even time slot when operating in the network mode. Even time slots are all
even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from zero to N-1, where N is the number
of time slots in the frame. The zero time slot is considered even. REDF is set when the contents of the
receive shift registers are transferred to the receive data registers. REDF is cleared when the DSP reads all
the enabled receive data registers or cleared by hardware, software, ESAI individual, or STOP resets. If
REDIE is set, an ESAI receive even slot data interrupt request is issued when REDF is set.
8.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10
When set, RODF indicates that the received data in the receive data registers of the enabled receivers have
arrived during an odd time slot when operating in the network mode. Odd time slots are all odd-numbered
slots (1, 3, 5, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the
frame. RODF is set when the contents of the receive shift registers are transferred to the receive data
registers. RODF is cleared when the DSP reads all the enabled receive data registers or cleared by
hardware, software, ESAI individual, or STOP resets.
8.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13
When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start
of the first time slot in the frame and cleared during all other time slots. Data written to a transmit data
register during the time slot when TFS is set is transmitted (in network mode), if the transmitter is enabled,