Freescale Semiconductor DSP56366 - Manual (Page 111)

HDI08 – DSP-Side Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 6-17
6.5.10 Host Interface DSP Core Interrupts
The HDI08 may request interrupt service from either the DSP core or the host processor. The DSP core
interrupts are internal and do not require the use of an external interrupt pin. When the appropriate interrupt
enable bit in the HCR is set, an interrupt condition caused by the host processor sets the appropriate bit in
the HSR, generating an interrupt request to the DSP core. The DSP core acknowledges interrupts caused
by the host processor by jumping to the appropriate interrupt service routine. The three possible interrupts
are as follows:
• Host command
• Transmit data register empty
• Receive data register full
Although there is a set of vectors reserved for host command use, the host command can access any
interrupt vector in the interrupt vector table. The DSP interrupt service routine must read or write the
appropriate HDI08 register (clearing HRDF or HTDE, for example) to clear the interrupt. In the case of
host command interrupts, the interrupt acknowledge from the DSP core program controller clears the
pending interrupt condition.
Figure 6-11 illustrates the HSR-HCR operation.
Table 6-7 DSP-Side Registers after Reset
Register
Name
Register
Data
Reset Type
HW
Reset
SW
Reset
IR
Reset
ST
Reset
HCR All bits 0 0 — —
HPCR All bits 0 0 — —
HSR HF[1:0] 0 0 — —
HCP 0 0 0 0
HTDE 1 1 1 1
HRDF 0 0 0 0
DMA 0 0 — —
HBAR BA[10:3] $80 $80 — —
HDDR DR[15:0] 0 0 — —
HDR D[15:0] — — — —
HORX HORX[23:0] empty empty empty empty
HOTX HOTX[23:0] empty empty empty empty
Note: A long dash (—) denotes that the register value is not affected by the specified reset.