Freescale Semiconductor DSP56366 - Manual (Page 107)

HDI08 – DSP-Side Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 6-13
6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1
If the HA8EN bit is set and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is used as host
address line 8 (HA8). If this bit is cleared and the HDI08 is used in multiplexed bus mode, then HA8/HA1
is configured as GPIO pin according to the value of HDDR and HDR registers. HA8EN is ignored when
the HDI08 is not in the multiplexed bus mode (HMUX=0).
6.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2
If the HA9EN bit is set and the HDI08 is used in multiplexed bus mode, then HA9/HA2 is used as host
address line 9 (HA9). If this bit is cleared and the HDI08 is used in multiplexed bus mode, then HA9/HA2
is configured as GPIO pin according to the value of HDDR and HDR registers. HA9EN is ignored when
the HDI08 is not in the multiplexed bus mode (HMUX=0).
6.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3
If the HCSEN bit is set, then HCS/HA10 is used as host chip select (HCS) in the non-multiplexed bus
mode (HMUX=0), and as host address line 10 (HA10) in the multiplexed bus mode (HMUX=1). If this bit
is cleared, then HCS/HA10 is configured as GPIO pin according to the value of HDDR and HDR registers.
6.5.6.5 HPCR Host Request Enable (HREN) Bit 4
The HREN bit controls the host request signals. If HREN is set and the HDI08 is in the single host request
mode (HDRQ=0 in the ICR), HOREQ/HTRQ is configured as the host request (HOREQ) output.
If HREN is set in the double host request mode (HDRQ=1 in the ICR), HOREQ/HTRQ is configured as
the host transmit request (HTRQ) output and HACK/HRRQ as the host receive request (HRRQ) output.
If HREN is cleared, HOREQ/HTRQ and HACK/HRRQ are configured as GPIO pins according to the
value of HDDR and HDR registers.
6.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5
The HAEN bit controls the HACK signal. In the single host request mode (HDRQ=0 in the ICR), if HAEN
and HREN are both set, HACK/HRRQ is configured as the host acknowledge (HACK) input. If HAEN or
HREN is cleared, HACK/HRRQ is configured as a GPIO pin according to the value of HDDR and HDR
registers. In the double host request mode (HDRQ=1 in the ICR), HAEN is ignored.
6.5.6.7 HPCR Host Enable (HEN) Bit 6
If the HEN bit is set, the HDI08 operation is enabled as Host Interface. If cleared, the HDI08 is not active,
and all the HDI08 pins are configured as GPIO pins according to the value of HDDR and HDR registers.
6.5.6.8 HPCR Reserved Bit 7
This bit is reserved. It reads as zero and should be written with zero for future compatibility.