Freescale Semiconductor DSP56366 - Manual (Page 40)

External Memory Expansion Port (Port A)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
2-6 Freescale Semiconductor
WR Output Tri-stated Write Enable — When the DSP is the bus master, WR is an active-low output
that is asserted to write external memory on the data bus (D0-D23).
Otherwise, WR is tri-stated.
TA Input Ignored Input Transfer Acknowledge — If the DSP is the bus master and there is no
external bus activity, or the DSP is not the bus master, the TA input is ignored.
The TA input is a data transfer acknowledge (DTACK) function that can extend
an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity)
may be added to the wait states inserted by the BCR by keeping TA
deasserted. In typical operation, TA is deasserted at the start of a bus cycle,
is asserted to enable completion of the bus cycle, and is deasserted before
the next bus cycle. The current bus cycle completes one clock period after TA
is asserted synchronous to the internal system clock. The number of wait
states is determined by the TA input or by the bus control register (BCR),
whichever is longer. The BCR can be used to set the minimum number of wait
states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the TAS bit in
the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
BR Output Output
(deasserted)
Bus Request — BR is an active-low output, never tri-stated. BR is asserted
when the DSP requests bus mastership. BR is deasserted when the DSP no
longer needs the bus. BR may be asserted or deasserted independent of
whether the DSP56364 is a bus master or a bus slave. Bus “parking” allows
BR to be deasserted even though the DSP56364 is the bus master. (See the
description of bus “parking” in the BB signal description.) The bus request
hold (BRH) bit in the BCR allows BR to be asserted under software control
even though the DSP does not need the bus. BR is typically sent to an
external bus arbitrator that controls the priority, parking, and tenure of each
master on the same external bus. BR is only affected by DSP requests for the
external bus, never for the internal bus. During hardware reset, BR is
deasserted and the arbitration is reset to the bus slave state.
Table 2-7 External Bus Control Signals (continued)
Signal Name Type
State during
Reset
Signal Description