Freescale Semiconductor DSP56366 - Manual (Page 145)

SHI Programming Considerations
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 7-21
It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data
reception in order to reset the receive FIFO to its initial (empty) state (e.g., when switching from transmit
to receive data).
The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared, and considered
if any of them is set. When asserted by the slave device, HREQ indicates that the external slave device is
ready for the next data transfer. As a result, the SPI master sends clock pulses for the full data word transfer.
HREQ is deasserted by the external slave device at the first clock pulse of the new data transfer. When
deasserted, HREQ prevents the clock generation of the next data word transfer until it is asserted again.
Connecting the HREQ line between two SHI-equipped DSPs, one operating as an SPI master device and
the other as an SPI slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ
should be disabled by clearing HRQE[1:0].
7.7.3 I
2
C Slave Mode
The I
2
C slave mode is entered by enabling the SHI (HEN=1), selecting the I
2
C mode (HI
2
C=1), and
selecting the slave mode of operation (HMST=0). In this operational mode the contents of HCKR are
ignored. When configured in the I
2
C slave mode, the SHI external pins operate as follows:
• SCK/SCL is the SCL serial clock input.
• MISO/SDA is the SDA open drain serial data line.
• MOSI/HA0 is the HA0 slave device address input.
• SS/HA2 is the HA2 slave device address input.
• HREQ is the Host Request output.
When the SHI is enabled and configured in the I
2
C slave mode, the SHI controller inspects the SDA and
SCL lines to detect a start event. Upon detection of the start event, the SHI receives the slave device
address byte and enables the slave device address recognition unit. If the slave device address byte was not
identified as its personal address, the SHI controller fails to acknowledge this byte by not driving low the
SDA line at the ninth clock pulse (ACK = 1). However, it continues to poll the SDA and SCL lines to detect
a new start event. If the personal slave device address was correctly identified, the slave device address
byte is acknowledged (ACK = 0 is sent) and a receive/transmit session is initiated according to the eighth
bit of the received slave device address byte (i.e., the R/W bit).
7.7.3.1 Receive Data in I
2
C Slave Mode
A receive session is initiated when the personal slave device address has been correctly identified and the
R/W bit of the received slave device address byte has been cleared. Following a receive initiation, data in
the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is
sent at the ninth clock pulse via the SDA line. Data is acknowledged bytewise, as required by the I
2
C bus
protocol, and is transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled
into IOSR. It is the responsibility of the programmer to select the correct number of bytes in an I
2
C frame
so that they fit in a complete number of words. For this purpose, the slave device address byte does not
count as part of the data; therefore, it is treated separately.