Freescale Semiconductor DSP56366 - Manual (Page 114)

HDI08 – External Host Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-20 Freescale Semiconductor
6.6.1.1 ICR Receive Request Enable (RREQ) Bit 0
In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), RREQ is used to enable host receive data requests via
the host request (HOREQ or HRRQ) signal when the receive data register full (RXDF) status bit in the
ISR is set. If RREQ is cleared, RXDF requests are disabled. If RREQ is set, the host request signal
(HOREQ or HRRQ) is asserted if RXDF is set.
In the DMA modes where HDM[2:0]=100 and (HM1 ≠0 or HM0≠0), RREQ must be set and TREQ must
be cleared to direct DMA transfers from DSP to host. In the other DMA modes, RREQ is ignored.
Table 6-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ signals.
6.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1
In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), TREQ is used to enable host transmit data requests
via the host request (HOREQ or HTRQ) signal when the transmit data register empty (TXDE) status bit
in the ISR is set. If TREQ is cleared, TXDE requests are disabled. If TREQ is set, the host request signal
(HOREQ or HTRQ) is asserted if TXDE is set.
In the DMA modes where HDM[2:0]=100 and (HM1 ≠0 or HM0≠0), TREQ must be set and RREQ must
be cleared to direct DMA transfers from host to DSP. In the other DMA modes, TREQ is ignored.
Table 6-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ signals.
7 6 5 4 3 2 1 0
For HDM[2:0]=000 INIT HLEND HF1 HF0 HDRQ TREQ RREQ
For HDM[2:0]=100 INIT HM1 HM0 HF1 HF0 TREQ RREQ
For HDM1=1 and/or HDM0=1 INIT HDM1 HDM0 HF1 HF0 TREQ RREQ
HDM[1:0] - These read-only bits reflect the value of the HDM[1:0] bits in the HCR.
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-12 Interface Control Register (ICR)