Freescale Semiconductor DSP56366 - Manual (Page 132)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
7-8 Freescale Semiconductor
Figure 7-6 SPI Data-To-Clock Timing Diagram
If CPOL is cleared, it produces a steady-state low value at the SCK pin of the master device whenever data
is not being transferred. If the CPOL bit is set, it produces a high value at the SCK pin of the master device
whenever data is not being transferred.
CPHA is used with the CPOL bit to select the desired clock-to-data relationship. The CPHA bit, in general,
selects the clock edge that captures data and allows it to change states. It has its greatest impact on the first
bit transmitted (MSB) in that it does or does not allow a clock transition before the data capture edge.
When the SHI is in slave mode and CPHA = 0, the SS line must be deasserted and asserted by the external
master between each successive word transfer. SS must remain asserted between successive bytes within
a word. The DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. However,
the data is transferred to the shift register for transmission only when SS is deasserted. HTDE is set when
the data is transferred from HTX to the shift register.
When the SHI is in slave mode and CPHA = 1, the SS line may remain asserted between successive word
transfers. The SS must remain asserted between successive bytes within a word. The DSP core should
write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift
register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred
from HTX to the shift register.
When the SHI is in master mode and CPHA = 0, the DSP core should write the next data word to HTX
when HTDE = 1, clearing HTDE. The data is transferred immediately to the shift register for transmission.
HTDE is set only at the end of the data word transmission.
NOTE
The master is responsible for deasserting and asserting the slave device SS
line between word transmissions.
Internal Strobe for Data Capture
MSB 6 5 4 3 2 1 LSB
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 1, CPHA = 1)
SS
SCK
SCK
SCK
SCK
MISO/
MOSI
AA0421