Freescale Semiconductor DSP56366 - Manual (Page 173)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 8-23
Hardware and software reset clear all the bits of the RCCR register.
8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0
The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver clock generator.
A divide ratio from 1 to 256 (RPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at
the receiver serial bit clock (SCKR) pin of the DSP. The bit clock output is also available internally for use
as the bit clock to shift the receive shift registers. The ESAI receive clock generator functional diagram is
shown in
Figure 8-3 .
8.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8
The RPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used
to extend the range of the prescaler for those cases where a slower bit clock is desired. When RPSR is set,
the fixed prescaler is bypassed. When RPSR is cleared, the fixed divide-by-eight prescaler is operational
(see
Figure 8-3 ). The maximum internally generated bit clock frequency is Fosc/4, the minimum internally
generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
NOTE
Do not use the combination RPSR=1 and RPM7-RPM0=$00, which causes
synchronization problems when using the internal DSP clock as source
(RHCKD=1 or RCKD=1).
8.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 9–13
The RDC4–RDC0 bits control the divide ratio for the programmable frame rate dividers used to generate
the receiver frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide
ratio may range from 2 to 32 (RDC[4:0]=00001 to 11111) for network mode. A divide ratio of one
(RDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32
(RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one (RDC[4:0]=00000)
provides continuous periodic data word transfers. A bit-length frame sync (RFSL=1) must be used in this
case
.
The ESAI frame sync generator functional diagram is shown in Figure 8-4 .
8.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17
The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit
clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock.
When the HCKR input is being driven from an external high frequency clock, the RFP3-RFP0 bits specify
an additional division ration in the clock divider chain. See
Table 8-6 for the specification of the divide
ratio. The ESAI high frequency generator functional diagram is shown in Figure 8-3 .