Freescale Semiconductor DSP56366 - Manual (Page 119)

HDI08 – External Host Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 6-25
written by the host processor. TXDE can be set by the host processor using the initialize feature. TXDE
may be used to assert the external HOREQ signal if the TREQ bit is set. Regardless of whether the TXDE
interrupt is enabled, TXDE indicates whether the TX registers are full and data can be latched in (so that
polling techniques may be used by the host processor).
6.6.3.3 ISR Transmitter Ready (TRDY) Bit 2
The TRDY status bit indicates that TXH:TXM:TXL and the HORX registers are empty.
TRDY=TXDE
•
HRDF
If TRDY is set, the data that the host processor writes to TXH:TXM:TXL is immediately transferred to
the DSP side of the HDI08. This feature has many applications. For example, if the host processor issues
a host command which causes the DSP core to read the HORX, the host processor can be guaranteed that
the data it just transferred to the HDI08 is what is being received by the DSP core.
6.6.3.4 ISR Host Flag 2 (HF2) Bit 3
The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the DSP side. HF2 can be changed
only by the DSP (see
Section 6.5.3.4, "HCR Host Flags 2,3 (HF2,HF3) Bits 3-4" ).
6.6.3.5 ISR Host Flag 3 (HF3) Bit 4
The HF3 bit in the ISR indicates the state of host flag 3 in the HCR on the DSP side. HF3 can be changed
only by the DSP (see
Section 6.5.3.4, "HCR Host Flags 2,3 (HF2,HF3) Bits 3-4" ).
6.6.3.6 ISR Reserved Bits 5-6
These bits are reserved. They read as zero and should be written with zero for future compatibility.
6.6.3.7 ISR Host Request (HREQ) Bit 7
The HREQ bit indicates the status of the external host request output signal (HOREQ) if HDRQ is cleared.
If HDRQ is set, it indicates the status of the external transmit and receive request output signals (HTRQ
and HRRQ).
The HREQ bit may be set from either or both of two conditions – either the receive byte registers are full
or the transmit byte registers are empty. These conditions are indicated by the ISR RXDF and TXDE status
bits, respectively. If the interrupt source has been enabled by the associated request enable bit in the ICR,
HREQ is set if one or more of the two enabled interrupt sources is set.
Table 6-14 Host Request Status (HREQ)
HREQ Status [HDRQ=0] Status [HDRQ=1]
0 HOREQ deasserted; no host processor interrupt is
requested HTRQ and HRRQ deasserted; no host processor
interrupts are requested
1 HOREQ asserted; a host processor interrupt is
requested HTRQ and/or HRRQ asserted; host processor
interrupts are requested