2 underrun error interrupt enable (xuie)-bit 1, 3 block transferred interrupt enable (xbie)-bit 2, 4 dax clock input select (xcs[1:0])-bits 3-4 – Freescale Semiconductor DSP56366 User Manual
Page 223: 5 dax start block (xsb)-bit 5, 6 xctr reserved bits-bits 6-23, 7 dax status register (xstr), Underrun error interrupt enable (xuie)—bit 1 -7, Block transferred interrupt enable (xbie)—bit 2 -7, Dax clock input select (xcs[1:0])—bits 3–4 -7, Dax start block (xsb)—bit 5 -7
DAX Internal Architecture
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
10-7
10.5.6.1
Audio Data Register Empty Interrupt Enable (XDIE)—Bit 0
When the XDIE bit is set, the audio data register empty interrupt is enabled and sends an interrupt request
signal to the DSP if the XADE status bit is set. When XDIE bit is cleared, this interrupt is disabled.
10.5.6.2
Underrun Error Interrupt Enable (XUIE)—Bit 1
When the XUIE bit is set, the underrun error interrupt is enabled and sends an interrupt request signal to
the DSP if the XAUR status bit is set. When XUIE bit is cleared, this interrupt is disabled.
10.5.6.3
Block Transferred Interrupt Enable (XBIE)—Bit 2
When the XBIE bit is set, the block transferred interrupt is enabled and sends an interrupt request signal
to the DSP if the XBLK and XADE status bits are set. When XBIE bit is cleared, this interrupt is disabled.
10.5.6.4
DAX Clock Input Select (XCS[1:0])—Bits 3–4
The XCS[1:0] bits select the source of the DAX clock and/or its frequency.
shows the
configurations selected by these bits. These bits should be changed only when the DAX is disabled.
10.5.6.5
DAX Start Block (XSB)—Bit 5
The XSB bit forces the DAX to start a new block. When this bit is set, the next frame will start with “Z”
preamble and will start a new block even though the current block was not finished. This bit is cleared
when the new block starts.
10.5.6.6
XCTR Reserved Bits—Bits 6-23
These XCTR bits are reserved. They read as 0 and should be written with 0 for future compatibility.
10.5.7
DAX Status Register (XSTR)
The XSTR is a 24-bit read-only register that contains the DAX status flags. The contents of the XSTR are
shown in
. XSTR is cleared by software reset, hardware reset an by the stop state. The XSTR
bits are described in the following paragraphs.
Table 10-3 Clock Source Selection
XCS1
XCS0
DAX Clock Source
0
0
DSP Core Clock (f = 1024
x
fs)
0
1
ACI Pin, f = 256
x
fs
1
0
ACI Pin, f = 384
x
fs
1
1
ACI Pin, f = 512
x
fs