Table d-3, D.4 interrupt source priorities (within an ipl) – Freescale Semiconductor DSP56366 User Manual

Page 318

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Interrupt Source Priorities (within an IPL)

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

D-10

Freescale Semiconductor

D.4

Interrupt Source Priorities (within an IPL)

Table D-3. Interrupt Sources Priorities Within an IPL

Priority

Interrupt Source

Level 3 (Nonmaskable)

Highest

Hardware RESET

Stack Error

Illegal Instruction

Debug Request Interrupt

Trap

Lowest

Non-Maskable Interrupt

Levels 0, 1, 2 (Maskable)

Highest

IRQA (External Interrupt)

IRQB (External Interrupt)

IRQC (External Interrupt)

IRQD (External Interrupt)

DMA Channel 0 Interrupt

DMA Channel 1 Interrupt

DMA Channel 2 Interrupt

DMA Channel 3 Interrupt

DMA Channel 4 Interrupt

DMA Channel 5 Interrupt

ESAI Receive Data with Exception Status

ESAI Receive Even Data

ESAI Receive Data

ESAI Receive Last Slot

ESAI Transmit Data with Exception Status

ESAI Transmit Last Slot

ESAI Transmit Even Data

ESAI Transmit Data

SHI Bus Error

SHI Receive Overrun Error

SHI Transmit Underrun Error

SHI Receive FIFO Full

SHI Transmit Data

SHI Receive FIFO Not Empty

HOST Command Interrupt

HOST Receive Data Interrupt

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