Freescale Semiconductor DSP56366 - Manual (Page 136)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
7-12 Freescale Semiconductor
It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR.
HCKFR is cleared during hardware reset and software reset.
7.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5
The read/write control bit HFIFO selects the receive FIFO size. When HFIFO is cleared, the FIFO has one
level. When HFIFO is set, the FIFO has 10 levels. It is recommended that an SHI individual reset be
generated (HEN cleared) before changing HFIFO. HFIFO is cleared during hardware reset and software
reset.
7.4.6.6 HCSR Master Mode (HMST)—Bit 6
The read/write control bit HMST determines the SHI operating mode. If HMST is set, the interface
operates in the master mode. If HMST is cleared, the interface operates in the slave mode. The SHI
supports a single-master configuration in both I
2
C and SPI modes.
When configured as an SPI master, the SHI drives the SCK line and controls the direction of the data lines
MOSI and MISO. The SS line must be held deasserted in the SPI master mode; if the SS line is asserted
when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set—see
Section 7.4.6.18, "Host Bus Error (HBER)—Bit 21" ).
When configured as an I
2
C master, the SHI controls the I
2
C bus by generating start events, clock pulses,
and stop events for transmission and reception of serial data.
It is recommended that an SHI individual reset be generated (HEN cleared) before changing HMST.
HMST is cleared during hardware reset and software reset.
7.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7
The read/write control bits HRQE[1:0] are used to control the HREQ pin. When HRQE[1:0] are cleared,
the HREQ pin is disabled and held in the high impedance state. If either of HRQE[1:0] are set and the SHI
is in a master mode, the HREQ pin becomes an input controlling SCK: deasserting HREQ suspends SCK.
If either of HRQE[1:0] are set and the SHI is in a slave mode, HREQ becomes an output and its operation
is defined in
Table 7-5 . HRQE[1:0] should be changed only when the SHI is idle (HBUSY = 0).
HRQE[1:0] are cleared during hardware reset and software reset.
Table 7-5 HREQ Function In SHI Slave Modes
HRQE1 HRQE0 HREQ Pin Operation
0 0 High impedance
0 1 Asserted if IOSR is ready to receive a new word
1 0 Asserted if IOSR is ready to transmit a new word
1 1 I
2
C: Asserted if IOSR is ready to transmit or receive
SPI: Asserted if IOSR is ready to transmit and receive