Freescale Semiconductor DSP56366 - Manual (Page 105)

HDI08 – DSP-Side Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 6-11
by the HDI08 hardware when the interrupt request is serviced by the DSP core. The host can clear HC,
which also clears HCP.
6.5.4.4 HSR Host Flags 0,1 (HF0,HF1) Bits 3-4
HF0 and HF1 bits are used as a general-purpose flags for host to DSP communication. HF0 and HF1 may
be set or cleared by the host. HF0 and HF1 reflect the status of host flags HF0 and HF1 in the ICR register
on the host side.
These two flags are not designated for any specific purpose but are general-purpose flags. They can be
used individually or as encoded pairs in a simple host to DSP communication protocol, implemented in
both the DSP and the host Processor software.
6.5.4.5 HSR Reserved Bits 5-6, 8-15
These bits are reserved. They read as zero and should be written with zero for future compatibility.
6.5.4.6 HSR DMA Status (DMA) Bit 7
The DMA status bit is set when the DMA mode of operation is enabled, and is cleared when the DMA
mode is disabled. The DMA mode is enabled under the following conditions:
• HCR bits HDM[2:0] = 100 and the host processor has enabled the DMA mode by setting either or
both the ICR bits HM1 and HM0
• Either or both of the HCR bits HDM1 and HDM0 have been set
When the DMA bit is zero, the channel not in use can be used for polled or interrupt operation by the DSP.
6.5.5 Host Base Address Register (HBAR)
The HBAR is used in multiplexed bus modes. This register selects the base address where the host side
registers are mapped into the bus address space. The address from the host bus is compared with the base
address as programmed in the base address register. If the addresses match, an internal chip select is
generated. The use of this register by the chip selectlogic is shown in
Figure 6-5 .
.
6.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7
These bits define the base address where the host side registers are mapped into the bus address space.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3
- Reserved bit. Read as 0. Should be written with 0, for future compatibility.
Figure 6-4 Host Base Address Register (HBAR) (X:$FFFFC5)