Freescale Semiconductor DSP56366 - Manual (Page 163)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 8-13
.
Hardware and software reset clear all the bits in the TCR register.
The TCR bits are described in the following paragraphs.
8.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0
TE0 enables the transfer of data from TX0 to the transmit shift register #0. When TE0 is set and a frame
sync is detected, the transmit #0 portion of the ESAI is enabled for that frame. When TE0 is cleared, the
transmitter #0 is disabled after completing transmission of data currently in the ESAI transmit shift
register. The SDO0 output is tri-stated, and any data present in TX0 is not transmitted (i.e., data can be
written to TX0 with TE0 cleared; but data is not transferred to the transmit shift register #0).
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE0 and setting it again disables the transmitter #0 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO0 pin remains in the high-impedance state.The on-demand mode transmit enable sequence
can be the same as the normal mode, or TE0 can be left enabled.
8.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1
TE1 enables the transfer of data from TX1 to the transmit shift register #1. When TE1 is set and a frame
sync is detected, the transmit #1 portion of the ESAI is enabled for that frame. When TE1 is cleared, the
transmitter #1 is disabled after completing transmission of data currently in the ESAI transmit shift
register. The SDO1 output is tri-stated, and any data present in TX1 is not transmitted (i.e., data can be
written to TX1 with TE1 cleared; but data is not transferred to the transmit shift register #1).
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable sequence
can be the same as the normal mode, or TE1 can be left enabled.
11 10 9 8 7 6 5 4 3 2 1 0
X:$FFFFB5 TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD TE5 TE4 TE3 TE2 TE1 TE0
23 22 21 20 19 18 17 16 15 14 13 12
TLIE TIE TEDIE TEIE TPR PADC TFSR TFSL TSWS4 TSWS3 TSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-5 TCR Register