Freescale Semiconductor DSP56366 - Manual (Page 144)

SHI Programming Considerations
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
7-20 Freescale Semiconductor
If a write to HTX occurs, its contents are transferred to IOSR between data word transfers. The IOSR data
is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP may write HTX with either
DSP instructions or DMA transfers if the HTDE status bit is set. If no writes to HTX occur, the contents
of HTX are not transferred to IOSR, so the data shifted out when receiving is the data present in the IOSR
at the time. The HRX FIFO contains valid receive data, which the DSP can read with either DSP
instructions or DMA transfers (if the HRNE status bit is set).
The HREQ output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is ready for
receive and the HRX FIFO is not full; this operation guarantees that the next received data word is stored
in the FIFO. The HREQ output pin, if enabled for transmit (HRQE[1:0] = 10), is asserted when the IOSR
is loaded from HTX with a new data word to transfer. If HREQ is enabled for both transmit and receive
(HRQE[1:0] = 11), it is asserted when the receive and transmit conditions are both true. HREQ is
deasserted at the first clock pulse of the next data word transfer. The HREQ line may be used to interrupt
the external master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as
an SPI master device and the other as an SPI slave device, enables full hardware handshaking if operating
with CPHA = 1.
The SS line should be kept asserted during a data word transfer. If the SS line is deasserted before the end
of the data word transfer, the transfer is aborted and the received data word is lost.
7.7.2 SPI Master Mode
The SPI master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode (HI
2
C = 0), and
selecting the master mode of operation (HMST = 1). Before enabling the SHI as an SPI master device, the
programmer should program the proper clock rate, phase and polarity in HCKR. When configured in the
SPI master mode, the SHI external pins operate as follows:
• SCK/SCL is the SCK serial clock output.
• MISO/SDA is the MISO serial data input.
• MOSI/HA0 is the MOSI serial data output.
• SS/HA2 is the SS input. It should be kept deasserted (high) for proper operation.
• HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by activating a GPIO pin
connected to its SS pin. However, the SS input pin of the SPI master device should be held deasserted
(high) for proper operation. If the SPI master device SS pin is asserted, the host bus error status bit (HBER)
is set. If the HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service the SHI
bus error interrupt.
In the SPI master mode the DSP must write to HTX to receive, transmit or perform a full-duplex data
transfer. Actually, the interface performs simultaneous data receive and transmit. The status bits of both
receive and transmit paths are active; however, the programmer may disable undesired interrupts and
ignore irrelevant status bits. In a data transfer, the HTX is transferred to IOSR, clock pulses are generated,
the IOSR data is shifted out (via MOSI) and received data is shifted in (via MISO). The DSP programmer
may write HTX (if the HTDE status bit is set) with either DSP instructions or DMA transfers to initiate
the transfer of the next word. The HRX FIFO contains valid receive data, which the DSP can read with
either DSP instructions or DMA transfers, if the HRNE status bit is set.