Freescale Semiconductor DSP56366 - Manual (Page 157)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 8-7
8.2.10 Frame Sync for Transmitter (FST)
FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the
synchronous mode (SYN=1) and for the transmitters only in asynchronous mode (SYN=0) (see
Table 8-2 ).
The direction of this pin is determined by the TFSD bit in the TCR register. When configured as an output,
this pin is the internally generated frame sync signal. When configured as an input, this pin receives an
external frame sync signal for the transmitters (and the receivers in synchronous mode).
FST may be programmed as a general-purpose I/O pin (PC4) when the ESAI FST function is not being
used.
8.2.11 High Frequency Clock for Transmitter (HCKT)
HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI interface. The
direction of this pin is determined by the THCKD bit in the TCCR register. In the asynchronous mode
(SYN=0), the HCKT pin operates as the high frequency clock input or output used by all enabled
transmitters. In the synchronous mode (SYN=1), it operates as the high frequency clock input or output
used by all enabled transmitters and receivers. When programmed as input this pin is used as an alternative
high frequency clock source to the ESAI transmitter rather than the DSP main clock. When programmed
as output it can serve as a high frequency sample clock (to external DACs for example) or as an additional
system clock. See
Table 8-2 .
HCKT may be programmed as a general-purpose I/O pin (PC5) when the ESAI HCKT function is not
being used.
8.2.12 High Frequency Clock for Receiver (HCKR)
HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI interface. The
direction of this pin is determined by the RHCKD bit in the RCCR register. In the asynchronous mode
(SYN=0), the HCKR pin operates as the high frequency clock input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as the serial flag 2 pin. For further information
on pin mode and definition, see
Table 8-9 and on receiver clock signals see Table 8-1 .
When this pin is configured as serial flag pin, its direction is determined by the RHCKD bit in the RCCR
register. When configured as the output flag OF2, this pin reflects the value of the OF2 bit in the SAICR
register, and the data in the OF2 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When configured as the input flag IF2, the data value at the pin is stored
in the IF2 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network
mode.
HCKR may be programmed as a general-purpose I/O pin (PC2) when the ESAI HCKR function is not
being used.
8.3 ESAI Programming Model
The ESAI can be viewed as five control registers, one status register, six transmit data registers, four
receive data registers, two transmit slot mask registers, two receive slot mask registers and a