Freescale Semiconductor DSP56366 - Manual (Page 140)

Characteristics Of The SPI Bus
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
7-16 Freescale Semiconductor
7.4.6.18 Host Bus Error (HBER)—Bit 21
The read-only status bit HBER indicates, when set, that an SHI bus error occurred when operating as a
master (HMST set). In I
2
C mode, HBER is set if the transmitter does not receive an acknowledge after a
byte is transferred; then a stop event is generated and transmission is suspended. In SPI mode, HBER is
set if SS is asserted; then transmission is suspended at the end of transmission of the current word. HBER
is cleared only by hardware reset, software reset, SHI individual reset, and during the stop state.
7.4.6.19 HCSR Host Busy (HBUSY)—Bit 22
The read-only status bit HBUSY indicates that the I
2
C bus is busy (when in the I
2
C mode) or that the SHI
itself is busy (when in the SPI mode). When operating in the I
2
C mode, HBUSY is set after the SHI detects
a start event and remains set until a stop event is detected. When operating in the slave SPI mode, HBUSY
is set while SS is asserted. When operating in the master SPI mode, HBUSY is set if the HTX register is
not empty or if the IOSR is not empty. HBUSY is cleared otherwise. HBUSY is cleared by hardware reset,
software reset, SHI individual reset, and during the stop state.
7.5 Characteristics Of The SPI Bus
The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK), and a Slave Select
line (SS). During an SPI transfer, a byte is shifted out one data pin while a different byte is simultaneously
shifted in through a second data pin. It can be viewed as two 8-bit shift registers connected together in a
circular manner, with one shift register on the master side and the other on the slave side. Thus the data
bytes in the master device and slave device are exchanged. The MISO and MOSI data pins are used for
transmitting and receiving serial data. When the SPI is configured as a master, MISO is the master data
input line, and MOSI is the master data output line. When the SPI is configured as a slave device, MISO
is the slave data output line, and MOSI is the slave data input line.
Clock control logic allows a selection of clock polarity and a choice of two fundamentally different
clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI
is configured as a master, the control bits in the HCKR select the appropriate clock rate, as well as the
desired clock polarity and phase format (see Figure 7-6).
The SS line allows selection of an individual slave SPI device; slave devices that are not selected do not
interfere with SPI bus activity (i.e., they keep their MISO output pin in the high-impedance state). When
the SHI is configured as an SPI master device, the SS line should be held high. If the SS line is driven low
when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set).
7.6 Characteristics Of The I
2
C Bus
The I
2
C serial bus consists of two bidirectional lines, one for data signals (SDA) and one for clock signals
(SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
NOTE
In the I
2
C bus specifications, the standard mode (100 kHz clock rate) and a
fast mode (400 kHz clock rate) are defined. The SHI can operate in either
mode.