Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 115)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 115
April 2014
Chapter 6
SystemVerilog Tutorials
This chapter discusses how to use the Mentor Verification IP Altera Edition master and slave
BFMs to verify slave and master DUT components.
In the Verifying a Slave DUT tutorial, the slave is an on-chip RAM model that is verified using
a master BFM and test program. In the Verifying a Master DUT tutorial, the master issues
simple write and read transactions that are verified using a slave BFM and test program.
Following this top-level discussion of how you verify a master and a slave component using the
Mentor Verification IP Altera Edition is a brief example of how to run Qsys, the powerful
system integration tool in Quartus
® II software. This procedure shows you how to use Qsys to
create a top-level DUT environment. For more details on this example, refer to “ Getting Started
with Qsys and the BFMs ” on page 353.
Note
Parameters to configure any optional signals, master BFM transaction issuing and slave
BFM acceptance capability, are set with the Qsys Parameter Editor. See “
Running the
Qsys Tool ” on page 356 for details of the Qsys Parameter Editor.
Verifying a Slave DUT
A slave DUT component is connected to a master BFM at the signal-level. A master test
program, written at the transaction-level, generates stimulus using the master BFM to verify the
slave DUT.
Figure 6-1 illustrates a typical top-level test bench environment.
Figure 6-1. Slave DUT Top-Level Test Bench Environment
Master
BFM On-chip
RAM slave
Master
Test
program
Top-level file