Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 405)

VHDL Test Programs
AXI4-Lite VHDL Slave BFM Test Program
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 405
April 2014
variable data : std_logic_vector(7 downto 0);
begin
loop
pop_transaction_id(read_trans, AXI4_QUEUE_ID_1, index, AXI4_PATH_4,
axi4_tr_if_4(index));
set_read_data_valid_delay(read_trans, AXI4_PATH_4,
axi4_tr_if_4(index));
get_read_addr(read_trans, 0, 0, byte_length, addr, index,
AXI4_PATH_4, axi4_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, 0, 0, byte_length, addr, data, index,
AXI4_PATH_4, axi4_tr_if_4(index));
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_read_addr(read_trans, 0, j, byte_length, addr, index,
AXI4_PATH_4, axi4_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, 0, j, byte_length, addr, data, index,
AXI4_PATH_4, axi4_tr_if_4(index));
end loop;
end if;
execute_read_data_phase(read_trans, index, AXI4_PATH_4,
axi4_tr_if_4(index));
end loop;
wait;
end process;
-- handle_write_addr_ready : write address ready through path 5
-- This method assert/de-assert the write address channel ready signal.
-- Assertion and de-assertion is done based on
m_wr_addr_phase_ready_delay
process
variable tmp_ready_delay : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, AXI4_PATH_5, axi4_tr_if_5(index));
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5, axi4_tr_if_5(index));
loop
wait until m_wr_addr_phase_ready_delay > 0;
tmp_ready_delay := m_wr_addr_phase_ready_delay;
execute_write_addr_ready(0, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
get_write_addr_cycle(index, AXI4_PATH_5, axi4_tr_if_5(index));
if(tmp_ready_delay > 1) then
for i in 0 to tmp_ready_delay-2 loop
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
end if;
execute_write_addr_ready(1, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
wait;
end process;
-- handle_read_addr_ready : read address ready through path 6
-- This method assert/de-assert the write address channel ready signal.