Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 50)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 50
SystemVerilog Master BFM
execute_write_addr_phase()
April 2014
execute_write_addr_phase()
This task executes a master write address phase previously created by the
create_write_transaction() function. This phase can be blocking (default) or nonblocking, as
defined by the transaction operation_mode field.
It sets the AWVALID protocol signal at the appropriate time defined by the transaction
address_valid_delay field.
Example
// Declare a local variable to hold the transaction record.
axi4_transaction write_trans;
// Create a write transaction with start address of 0 and assign
// it to the local write_trans variable.
write_trans = bfm.create_write_transaction(0);
....
// Execute the write_trans transaction.
bfm.execute_transaction(write_trans);
Prototype
task automatic execute_write_addr_phase
(
axi4_transaction trans
);
Arguments trans The axi4_transaction record.
Returns None