Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 387)

SystemVerilog Test Programs
SystemVerilog AXI4-Lite Master BFM Test Program
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 387
April 2014
// Write data value 3 on byte lane 3 to address 3.
trans = bfm.create_write_transaction(3);
trans.set_data_words(32'h0300_0000,0);
trans.set_write_strobes(4'b1000,0);
$display ( "@ %t, master_test_program: Writing data (3) to address
(3)", $time);
bfm.execute_transaction(trans);
// Write data value 4 to address 0 on byte lane 0.
trans = bfm.create_write_transaction(0);
trans.set_data_words(32'h0000_0004,0);
trans.set_write_strobes(4'b0001,0);
trans.set_write_data_mode(AXI4_DATA_WITH_ADDRESS);
$display ( "@ %t, master_test_program: Writing data (4) to address
(0)", $time);
bfm.execute_transaction(trans);
// 4 x Reads
// Read data from address 1.
trans = bfm.create_read_transaction(1);
bfm.execute_transaction(trans);
data_word = trans.get_data_words();
if (data_word[15:8] == 8'h01)
$display ( "@ %t, master_test_program: Read correct data (1) at
address (1)", $time);
else
$display ( "@ %t master_test_program: Error: Expected data (1) at
address 1, but got %d", $time, data_word[15:8]);
// Read data from address 2.
trans = bfm.create_read_transaction(2);
bfm.execute_transaction(trans);
data_word = trans.get_data_words();
if (data_word[23:16] == 8'h02)
$display ( "@ %t, master_test_program: Read correct data (2) at
address (2)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data (2) at
address 2, but got %d", $time, data_word[23:16]);
// Read data from address 3.
trans = bfm.create_read_transaction(3);
bfm.execute_transaction(trans);
data_word = trans.get_data_words();
if (data_word[31:24] == 8'h03)
$display ( "@ %t, master_test_program: Read correct data (3) at
address (3)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data (3) at
address 3, but got %d", $time, data_word[31:24]);
// Read data from address 0.
trans = bfm.create_read_transaction(0);