Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 351)

VHDL Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 351
April 2014
Example 11-18. handle_write_addr_ready
-- handle_write_addr_ready : write address ready through path 5
-- This method assert/de-assert the write address channel ready signal.
-- Assertion and de-assertion is done based on
m_wr_addr_phase_ready_delay
process
variable tmp_ready_delay : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, AXI4_PATH_5, axi4_tr_if_5(index));
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5, axi4_tr_if_5(index));
loop
wait until m_wr_addr_phase_ready_delay > 0;
tmp_ready_delay := m_wr_addr_phase_ready_delay;
execute_write_addr_ready(0, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
get_write_addr_cycle(index, AXI4_PATH_5, axi4_tr_if_5(index));
if(tmp_ready_delay > 1) then
for i in 0 to tmp_ready_delay-2 loop
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
end if;
execute_write_addr_ready(1, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
wait;
end process;
handle_read_addr_ready
The handle_read_addr_ready process handles the ARREADY signal for the read address
channel. It uses a unique path identifier to work concurrently with other processes. The
handle_read_addr_ready process code works in a similar way to that previously described for
the
handle_write_addr_ready process. Refer to the “ AXI4-Lite VHDL Slave BFM Test
Program ” on page 401 for the complete handle_read_addr_ready code listing.
handle_write_data_ready
The handle_write_data_ready process handles the WREADY signal for the write data channel.
It uses a unique path identifier to work concurrently with other processes.
The handle_write_data_ready process code works in a similar way to that previously described
for the
handle_write_addr_ready process. Refer to “ AXI4-Lite VHDL Slave BFM Test
Program ” on page 401 for the complete handle_write_data_ready code listing.