Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 58)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 58
SystemVerilog Master BFM
get_write_data_ready()
April 2014
get_write_data_ready()
This blocking task returns the value of the write data channel WREADY signal using the ready
argument. It will block for one ACLK period.
Example
// Get the value of the WREADY signal
bfm.get_write_data_ready();
Prototype task automatic get_write_data_ready
(
output bit ready
);
Arguments ready The value of the WREADY signal.
Returns None