Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual

Page 379

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AXI4-Lite Assertions

Mentor Verification IP AE AXI4-Lite User Guide, V10.3

379

April 2014

AXI4-
60139

AXI4_RID_UNKN

RID has an X value/RID has a Z
value.

AXI4-
60140

AXI4_RLAST_CHANGED_BEFORE_
RREADY

The value of RLAST has changed
from its initial value between the time
RVALID was asserted and before
RREADY was asserted.

A3.2.1

AXI4-
60141

AXI4_RLAST_UNKN

RLAST has an X value/RLAST has a
Z value.

AXI4-
60142

AXI4_RREADY_NOT_ASSERTED_
AFTER_RVALID

Once RVALID has been asserted
RREADY should be asserted in
config_max_latency_RVALID_assert
ion_to_RREADY
clock periods.

AXI4-
60143

AXI4_RREADY_UNKN

RREADY has an X value/RREADY
has a Z value.

AXI4-
60144

AXI4_RRESP_UNKN

RRESP has an X value/RRESP has
a Z value.

AXI4-
60145

AXI4_RUSER_CHANGED_BEFORE_
RREADY

The value of RUSER has changed
from its initial value between the time
RVALID was asserted and before
RREADY was asserted.

A3.2.1

AXI4-
60146

AXI4_RUSER_UNKN

RUSER has an X value/RUSER has
a Z value.

AXI4-
60147

AXI4_RVALID_DEASSERTED_
BEFORE_RREADY

RVALID has been de-asserted
before RREADY was asserted.

A3.2.1

AXI4-
60148

AXI4_RVALID_HIGH_EXITING_
RESET

RVALID should have been driven
low when exiting reset.

A3.1.2

AXI4-
60149

AXI4_RVALID_UNKN

RVALID has an X value/RVALID has
a Z value.

AXI4-
60150

AXI4_SLV_ERR_RESP_FOR_

READ

Slave has detected an error for this
read transfer (signaled by
AXI4_SLVERR).

AXI4-
60151

AXI4_SLV_ERR_RESP_FOR_WRITE

Slave has detected an error for this
write transfer (signaled by
AXI4_SLVERR).

AXI4-
60152

AXI4_TIMEOUT_WAITING_FOR_READ_RESP
ONSE

Timed-out waiting for a read
response.

A4.6

AXI4-
60153

AXI4_TIMEOUT_WAITING_FOR_
WRITE_RESPONSE

Timed-out waiting for a write
response.

A4.6

AXI4-
60154

AXI4_UNALIGNED_ADDRESS_FOR_
EXCLUSIVE_READ

Exclusive read accesses must have
address aligned to the total number
of bytes in the transaction.

A7.2.4

AXI4-
60155

AXI4_UNALIGNED_ADDR_FOR_
WRAPPING_READ_BURST

Wrapping bursts must have address
aligned to the start of the read
transfer.

A3.4.1

Table A-1. AXI4 Assertions (cont.)

Error
Code

Error Name

Description

Property
Ref

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