Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 153)

VHDL Master BFM
Master BFM Configuration
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 153
April 2014
A master BFM has configuration fields that you can set via the set_config() function to
configure timeout factors, setup and hold times, and so on. You can also get the value of a
configuration field via the
get_config() procedures. Table 8-2 describes the full list of
configuration fields.
READ_ISSUING_
CAPABILITY The maximum number of outstanding read transactions
that can be issued from the Master BFM. This parameter
is set with the Qsys Parameter Editor. See “
Running the
Qsys Tool ” on page 356. for details.
Default: 16.
WRITE_ISSUING_
CAPABILITY The maximum number of outstanding write transactions
that can be issued from the Master BFM. This parameter
is set with the Qsys Parameter Editor. See “
Running the
Qsys Tool ” on page 356. for details.
Default: 16.
COMBINED_ISSUING_
CAPABILITY The maximum number of outstanding combined read and
write transactions that can be issued from the Master
BFM. This parameter is set with the Qsys Parameter
Editor. See “
Running the Qsys Tool ” on page 356. for
details.
Default: 16.
Table 8-2. Master BFM Configuration
Configuration Field Description
Timing Variables
AXI4_CONFIG_SETUP_TIME The setup-time prior to the active edge
of ACLK, in units of simulator time-
steps for all signals.
1
Default: 0.
AXI4_CONFIG_HOLD_TIME The hold-time after the active edge of
ACLK, in units of simulator time-steps
for all signals.
1
Default: 0.
AXI4_CONFIG_MAX_TRANSACTION_TIME_
FACTOR The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI4_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
Table 8-1. Master BFM Signal Width Parameters (cont.)
Signal Width Parameter Description