Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 131)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 131
April 2014
Initial Block
In an initial block, the slave test program configures the maximum number of outstanding read
and write transactions before waiting for the ARESETn signal to be deactivated. The following
positive edge of ACLK starts the processing of any read or write transactions, and the handling
of the channel *READY signals in a fork-join block, as shown in
Example 6-17 .
Example 6-17. Initialization and Transaction Processing
initial
begin
// Initialisation
bfm.wait_on(AXI4_RESET_0_TO_1);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
// Traffic generation
fork
process_read;
process_write;
handle_write_addr_ready;
handle_read_addr_ready;
handle_write_data_ready;
join
end
process_read()
The process_read() task loops forever, processing read transactions as they occur from the
master. A local transaction variable read_trans of type axi4_transaction is defined to hold a
record of the read transaction while it is being processed. A slave transaction is created by
calling the
create_slave_transaction() function and assigned to the read_trans record.
The subsequent fork-join_none block performs a nonblocking statement so that the
process_read() task can begin again to create another read transaction record and get another
read address phase before the current read transaction has completed. This permits concurrent
read transactions to occur if the master issues a series of read address phases before any
previous read transactions have completed.