Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 188)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 188
VHDL Master BFM
get_write_response_valid_delay()
April 2014
get_write_response_valid_delay()
This nonblocking procedure gets the write_response_valid_delay field for a transaction that is
uniquely identified by the transaction_id field previously created by the
create_write_transaction() procedure.
Example
-- Create a write transaction with start address of 0.
-- Creation returns tr_id to identify the transaction.
create_write_transaction(0, tr_id, bfm_index, axi4_tr_if_0(bfm_index));
....
-- Get the write response channel BVALID delay of the tr_id transaction.
get_write_response_valid_delay(write_response_valid_delay, tr_id,
bfm_index, axi4_tr_if_0(bfm_index));
Prototype get_write_response_valid_delay
(
write_response_valid_delay: out integer;
transaction_id : in integer;
bfm_id : in integer;
path_id : in axi4_path_t; --optional
signal tr_if : inout axi4_vhd_if_struct_t
);
Arguments write_response_valid_delay Write data channel BVALID delay measured in ACLK
cycles for this transaction.
transaction_id Transaction identifier. Refer to “ Overloaded Procedure
Common Arguments ” on page 151 for more details.
bfm_id BFM identifier. Refer to “ Overloaded Procedure Common
Arguments ” on page 151 for more details.
path_id (Optional) Parallel process path identifier:
AXI4_PATH_0
AXI4_PATH_1
AXI4_PATH_2
AXI4_PATH_3
AXI4_PATH_4
Refer to “ Overloaded Procedure Common Arguments ” on
page 151 for more details.
tr_if Transaction signal interface. Refer to “ Overloaded
Procedure Common Arguments ” on page 151 for more
details.
Returns write_response_valid_delay