Assertion configuration, Systemverilog master api – Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual
Page 43
SystemVerilog Master BFM
SystemVerilog Master API
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
43
April 2014
Note
The built-in BFM assertions are independent of programming language and simulator.
Assertion Configuration
By default, all built-in assertions are enabled in the master AXI4-Lite BFM. To globally disable
them in the master BFM, use the
command as the following example illustrates:
set_config(AXI4_CONFIG_ENABLE_ALL_ASSERTIONS,0)
Alternatively, you can disable individual built-in assertions by using a sequence of
and
commands on the respective assertion. For example, to disable assertion
checking for the AWADDR signal changing between the AWVALID and AWREADY
handshake signals, use the following sequence of commands:
// Define a local bit vector to hold the value of the assertion bit vector
bit [255:0] config_assert_bitvector;
// Get the current value of the assertion bit vector
config_assert_bitvector = bfm.get_config(AXI4_CONFIG_ENABLE_ASSERTION);
// Assign the AXI4_AWADDR_CHANGED_BEFORE_AWREADY assertion bit to 0
config_assert_bitvector[AXI4_AWADDR_CHANGED_BEFORE_AWREADY] = 0;
// Set the new value of the assertion bit vector
bfm.set_config(AXI4_CONFIG_ENABLE_ASSERTION, config_assert_bitvector);
Note
Do not confuse the AXI4_CONFIG_ENABLE_ASSERTION bit vector with the
AXI4_CONFIG_ENABLE_ALL_ASSERTIONS global enable/disable.
To re-enable the AXI4_AWADDR_CHANGED_BEFORE_AWREADY assertion, follow the
above code sequence and assign the assertion within the
AXI4_CONFIG_ENABLE_ASSERTION bit vector to 1.
For a complete listing of AXI4-Lite assertions, refer to “
SystemVerilog Master API
This section describes the SystemVerilog master API.