Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 401)

VHDL Test Programs
AXI4-Lite VHDL Slave BFM Test Program
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 401
April 2014
end master_test_program_a;
AXI4-Lite VHDL Slave BFM Test Program
The following code example contains a simple slave test program that shows the slave BFM
API being used to communicate with a master and create stimulus. This test program is
discussed further in “
SystemVerilog Tutorials ” on page 115.
--
*************************************************************************
--
-- Copyright 2007-2014 Mentor Graphics Corporation
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
-- THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
-- SUBJECT TO LICENSE TERMS.
--
--
*************************************************************************
--
-- This is a simple example of an AXI Slave to demonstrate the
mgc_axi4_slave BFM configured as axi4lite usage.
--
-- This is a fairly generic slave which handles almost all write and read
transaction
-- scenarios from master. It handles write data with address as well as
data after address
-- both.
--
-- This slave code is divided in two parts, one which user might need to
edit to change slave
-- mode (Transaction/burst or Phase level) and memory handling.
-- Out of the code which is grouped as user do not need to edit, could be
edited for achieving
-- required phase valid/ready delays.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.all;
use work.mgc_axi4_bfm_pkg.all;
entity slave_test_program is
generic (AXI4_ADDRESS_WIDTH : integer := 32;
AXI4_RDATA_WIDTH : integer := 32;
AXI4_WDATA_WIDTH : integer := 32;
index : integer range 0 to 511 := 0
);
end slave_test_program;
architecture slave_test_program_a of slave_test_program is