Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 123)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 123
April 2014
handle_read_data_ready()
The handle_read_data_ready() task handles the RREADY signal for the read data channel. It
delays the assertion of the RREADY signal based on the settings of
master_ready_delay_mode
and m_rd_data_phase_ready_delay . The handle_read_data_ready() task code is similar in
operation to the handle_write_resp_ready() task. Refer to “ SystemVerilog AXI4-Lite Master
BFM Test Program ” on page 385 for the complete handle_read_data_ready() code listing.
Verifying a Master DUT
A master DUT component is connected to a slave BFM at the signal-level. A slave test program,
written at the transaction-level, generates stimulus via the slave BFM to verify the master DUT.
Figure 6-4 illustrates a typical top-level test bench environment.
Figure 6-4. Master DUT Top-Level Test Bench Environment
In this example, the slave test program is a simple memory model.
A top-level file instantiates and connects all the components required to test and monitor the
DUT, and controls the system clock (ACLK) and reset (ARESETn) signals.
BFM Slave Test Program
The slave test program is a memory model that contains two APIs: a Basic Slave API Definition
and an Advanced Slave API Definition .
The Basic Slave API Definition allows you to create a wide range of stimulus scenarios to test a
master DUT. This API definition simplifies the creation of slave stimulus based on the default
response of OKAY to master read and write transactions. The
Advanced Slave API Definition
allows you to create additional response scenarios to transactions.
Slave
BFM Master
DUT
Slave
test
program
Top-level file