Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 344)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 344
VHDL Tutorials
Verifying a Master DUT
April 2014
set_read_data_valid_delay()
The set_read_data_valid_delay() procedure has two prototypes (path_id is optional), and
configures the RVALID signal to be delayed by a number of ACLK cycles with the effect of
delaying the start of a read data phase (beat). The delay value of the RVALID signal is stored in
the data_valid_delay transaction field.
The code below shows the RVALID signal delay set to two ACLK periods. You may edit this
function to change the RVALID signal delay.
Example 11-12. set_read_data_valid_delay()
-- Procedure : set_read_data_valid_delay
-- This will set the ready delay for write data phase
procedure set_read_data_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t) is
variable burst_length : integer;
begin
set_data_valid_delay(2, id, index, tr_if);
end set_read_data_valid_delay;
Note
In addition to the above variables and procedures, you can configure other aspects of the
AXI4-Lite Slave BFM by using these procedures:
“set_config() ” on page 218 and
“get_config() ” on page 220.
Using the Basic Slave Test Program API
There is a set of variables and procedures that you can use to create stimulus scenarios based on
a memory-model slave with a minimal amount of editing, as described in “
Basic Slave API
Definition ” on page 341.
Consider the following configuration when using the slave test program.
Advanced Slave API Definition
Note
You are not required to edit the following Advance Slave API unless you require a
different response than the default (OKAY) response.
The remaining section of this tutorial presents a walk-through of the Advanced Slave API in the
slave test program. It consists of five main processes—
process_write , process_read ,
handle_write , handle_response, and handle_read —in the slave test program, as shown in
Figure 11-3 . There are additional handle_write_addr_ready , handle_read_addr_ready , and
handle_write_data_ready processes to handle the handshake AWREADY, ARREADY, and
WREADY signals, respectively.