Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 404)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 404
VHDL Test Programs
AXI4-Lite VHDL Slave BFM Test Program
April 2014
get_write_addr_data(write_trans, 0, 0, byte_length, addr, data,
index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_write_addr_data(write_trans, 0, j, byte_length, addr, data,
index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
end loop;
end if;
push_transaction_id(write_trans, AXI4_QUEUE_ID_2, index,
AXI4_PATH_1, axi4_tr_if_1(index));
end loop;
wait;
end process;
-- handle_response : write response phase through path 2
-- This method sends the write response phase
process
variable write_trans: integer;
begin
loop
pop_transaction_id(write_trans, AXI4_QUEUE_ID_2, index, AXI4_PATH_2,
axi4_tr_if_2(index));
set_wr_resp_valid_delay(write_trans, AXI4_PATH_2,
axi4_tr_if_2(index));
execute_write_response_phase(write_trans, index, AXI4_PATH_2,
axi4_tr_if_2(index));
end loop;
wait;
end process;
-- process_read : read address phase through path 3
-- This process keep receiving read address phase and push the
transaction into queue through
-- push_transaction_id API.
process
variable read_trans: integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, AXI4_PATH_3, axi4_tr_if_3(index));
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_3, axi4_tr_if_3(index));
loop
create_slave_transaction(read_trans, index, AXI4_PATH_3,
axi4_tr_if_3(index));
get_read_addr_phase(read_trans, index, AXI4_PATH_3,
axi4_tr_if_3(index));
push_transaction_id(read_trans, AXI4_QUEUE_ID_1, index, AXI4_PATH_3,
axi4_tr_if_3(index));
end loop;
wait;
end process;
-- handle_read : read data and response through path 4
-- This process reads data from memory and send read data/response
process
variable read_trans: integer;
variable byte_length : integer;
variable addr : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);