Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 215)

VHDL Slave BFM
Slave BFM Configuration
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 215
April 2014
AXI4_CONFIG_HOLD_TIME The hold-time after the active edge of
ACLK, in units of simulator time-steps
for all signals.
1
Default: 0.
AXI4_CONFIG_MAX_TRANSACTION_
TIME_FACTOR The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI4_CONFIG_BURST_TIMEOUT_
FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
AXI4_CONFIG_MAX_LATENCY_
AWVALID_ASSERTION_TO_AWREADY The maximum timeout duration from the
assertion of AWVALID to the assertion
of AWREADY in clock periods (default
10000).
AXI4_CONFIG_MAX_LATENCY_
ARVALID_ASSERTION_TO_ARREADY The maximum timeout duration from the
assertion of ARVALID to the assertion
of ARREADY in clock periods (default
10000).
AXI4_CONFIG_MAX_LATENCY_RVALID_
ASSERTION_TO_RREADY The maximum timeout duration from the
assertion of RVALID to the assertion of
RREADY in clock periods (default
10000).
AXI4_CONFIG_MAX_LATENCY_BVALID_
ASSERTION_TO_BREADY The maximum timeout duration from the
assertion of BVALID to the assertion of
BREADY in clock periods (default
10000).
AXI4_CONFIG_MAX_LATENCY_WVALID_
ASSERTION_TO_WREADY The maximum timeout duration from the
assertion of WVALID to the assertion of
WREADY in clock periods (default
10000).
Slave Attributes
AXI4_CONFIG_AXI4LITE_axi4 Configures the AXI4 slave BFM to be
AXI4-Lite compatible.
0 = disabled (default)
1 = enabled
AXI4_CONFIG_SLAVE_START_ADDR Configures the start address map for the
slave.
AXI4_CONFIG_SLAVE_END_ADDR Configures the end address map for the
slave.
Table 9-2. Slave BFM Configuration (cont.)
Configuration Field Description