Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 134)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 134
SystemVerilog Tutorials
Verifying a Master DUT
April 2014
WSTRB write strobes signal. There is an additional write response phase that is required for the
write response channel, as shown in
Example 6-21 .
Example 6-21. handle_write()
// Task : handle_write
// This method receive write data burst or phases for write transaction
// depending upon slave working mode, write data to memory and then send
// response
task automatic handle_write(input axi4_transaction write_trans);
addr_t addr[];
bit [7:0] data[];
bit last;
bfm.get_write_data_phase(write_trans,0,last);
void'(bfm.get_write_addr_data(write_trans, 0, addr, data));
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
set_wr_resp_valid_delay(write_trans);
bfm.execute_write_response_phase(write_trans);
endtask
handle_write_addr_ready()
The handle_write_addr_ready() task handles the AWREADY signal for the write address
channel. In a forever loop, it delays the assertion of the AWREADY signal based on the settings
of the
slave_ready_delay_mode and m_wr_resp_phase_ready_delay as shown in
Example 6-22 .
If the slave_delay_ready_mode = AXI4_VALID2READY, then the AWREADY signal is
deasserted using the nonblocking call to the
execute_write_data_ready() task and waits for a
write channel address phase to occur with a call to the blocking get_write_addr_cycle() task. A
received write address phase indicates that the AWVALID signal has been asserted, triggering
the starting point for the delay of the AWREADY signal by the number of ACLK cycles
defined by
m_wr_addr_phase_ready_delay . Another call to the execute_write_addr_ready()
task to assert the AWREADY signal completes the AWREADY handling. The
seen_valid_ready flag is set to indicate the end of a address phase when both AWVALID and
AWREADY are asserted.
If the slave_delay_ready_mode = AXI4_TRANS2READY, then a check of the
seen_valid_ready flag is performed to indicate that a previous write address phase has
completed. If a write address phase is still active (indicated by either AWVALID or
AWREADY not asserted), then the code waits until the previous write address phase has
completed. The AWREADY signal is then deasserted using the nonblocking call to the
execute_write_addr_ready() task and waits for the number of ACLK cycles defined by
m_wr_addr_phase_ready_delay . A nonblocking call to the execute_write_addr_ready() task to
assert the AWREADY signal completes the AWREADY handling. The seen_valid_ready flag
is cleared to indicate that only AWREADY has been asserted.