Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 42)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 42
SystemVerilog Master BFM
Master Assertions
April 2014
1.
Refer to Master Timing and Events for details of simulator time-steps.
Master Assertions
Each master BFM performs protocol error checking using the built-in assertions.
AXI4_CONFIG_MAX_LATENCY_RVALID_
ASSERTION_TO_RREADY The maximum timeout duration from
the assertion of RVALID to the
assertion of RREADY in clock periods.
Default: 10000.
AXI4_CONFIG_MAX_LATENCY_BVALID_
ASSERTION_TO_BREADY The maximum timeout duration from
the assertion of BVALID to the
assertion of BREADY in clock periods.
Default: 10000.
AXI4_CONFIG_MAX_LATENCY_WVALID_
ASSERTION_TO_WREADY The maximum timeout duration from
the assertion of WVALID to the
assertion of WREADY in clock
periods. Default 10000.
Master Attributes
AXI4_CONFIG_AXI4LITE_axi4 Configures the AXI4 master BFM to be
AXI4-Lite compatible.
0 = disabled (default)
1 = enabled
Slave Attributes
AXI4_CONFIG_SLAVE_START_ADDR Configures the start address map for
the slave.
AXI4_CONFIG_SLAVE_END_ADDR Configures the end address map for the
slave.
Error Detection
AXI4_CONFIG_ENABLE_ALL_ASSERTIONS Global enable/disable of all assertion
checks in the BFM.
0 = disabled
1 = enabled (default)
AXI4_CONFIG_ENABLE_ASSERTION Individual enable/disable of assertion
check in the BFM.
0 = disabled
1 = enabled (default)
Table 3-2. Master BFM Configuration (cont.)
Configuration Field Description