Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 14)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 14
April 2014
List of Figures
Figure 1-1. Execute Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 1-2. Master Write Transaction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 1-3. Slave Write Transaction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 1-4. Master Read Transaction Phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 1-5. Slave Read Transaction Phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-1. SystemVerilog BFM Internal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5-1. Inline Monitor Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 6-1. Slave DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 6-2. master_ready_delay_mode = AXI4_VALID2READY . . . . . . . . . . . . . . . . . . . 117
Figure 6-3. master_ready_delay_mode = AXI4_TRANS2READY . . . . . . . . . . . . . . . . . . . 117
Figure 6-4. Master DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 6-5. slave_ready_delay_mode = AXI4_VALID2READY . . . . . . . . . . . . . . . . . . . . 127
Figure 6-6. slave_ready_delay_mode = AXI4_TRANS2READY . . . . . . . . . . . . . . . . . . . . 128
Figure 6-7. Slave Test Program Advanced API Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 7-1. VHDL BFM Internal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 10-1. Inline Monitor Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 11-1. Slave DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . . 335
Figure 11-2. Master DUT Top-Level Test Bench Environment . . . . . . . . . . . . . . . . . . . . . . 340
Figure 11-3. Slave Test Program Advanced API Processes . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 12-1. Copy the Contents of qsys-examples from the Installation Folder . . . . . . . . . . 354
Figure 12-2. Paste qsys-examples from Installation to Work Folder . . . . . . . . . . . . . . . . . . 355
Figure 12-3. Select Qsys from the Quartus II Software Top-Level Menu . . . . . . . . . . . . . . 356
Figure 12-4. Open the ex1_back_to_back_sv.qsys Example . . . . . . . . . . . . . . . . . . . . . . . . . 356
Figure 12-5. Show System With Qsys Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 12-6. System With Qsys Interconnect Parameters Tab . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 12-7. Qsys Generation Window Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 12-8. Select the Work Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361