Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 386)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 386
SystemVerilog Test Programs
SystemVerilog AXI4-Lite Master BFM Test Program
April 2014
/////////////////////////////////////////////////
// Code user could edit according to requirements
/////////////////////////////////////////////////
// Variable : m_wr_resp_phase_ready_delay
int m_wr_resp_phase_ready_delay = 2;
// Variable : m_rd_data_phase_ready_delay
int m_rd_data_phase_ready_delay = 2;
// Master ready delay mode seclection : default it is VALID2READY
axi4_master_ready_delay_mode_e master_ready_delay_mode =
AXI4_VALID2READY;
initial
begin
axi4_transaction trans;
bit [AXI4_WDATA_WIDTH-1:0] data_word;
/*******************
** Initialisation **
*******************/
bfm.wait_on(AXI4_RESET_0_TO_1);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
/*******************
** **
*******************/
fork
handle_write_resp_ready;
handle_read_data_ready;
join_none
/************************
** Traffic generation: **
************************/
// 4 x Writes
// Write data value 1 on byte lanes 1 to address 1.
trans = bfm.create_write_transaction(1);
trans.set_data_words(32'h0000_0100,0);
trans.set_write_strobes(4'b0010,0);
$display ( "@ %t, master_test_program: Writing data (1) to address
(1)", $time);
// By default it will run in Blocking mode
bfm.execute_transaction(trans);
// Write data value 2 on byte lane 2 to address 2.
trans = bfm.create_write_transaction(2);
trans.set_data_words(32'h0002_0000,0);
trans.set_write_strobes(4'b0100,0);
trans.set_write_data_mode(AXI4_DATA_WITH_ADDRESS);
$display ( "@ %t, master_test_program: Writing data (2) to address
(2)", $time);
bfm.execute_transaction(trans);