Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 358)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 358
Getting Started with Qsys and the BFMs
Setting Up Simulation from the Windows GUI
April 2014
4. Click the System drop-down menu on the main Qsys toolbar, and select Show System
With Qsys Interconnect to open the System With Qsys Interconnect options window, as
shown in
Figure 12-6 .
5. Select a BFM within the Hierarchy pane of the System With Qsys Interconnect window,
in this case the mgc_axi4lite_slave_0. Click the Parameters tab to reveal the parameter
editor to review and change the selected BFM parameters.
Note
Placing the mouse pointer over a parameter name, or its value, opens a documentation
popup for the parameter. Parameter documentation is also available by clicking the
Documentation button.
Figure 12-6. System With Qsys Interconnect Parameters Tab
6. Close the System With Qsys Interconnect window after your parameter edits are
complete.
7. Click the Generate drop-down menu on the main Qsys toolbar, and select Generate
HDL to open the Generation options window.
8. Specify the Generation window options, as shown in Figure 12-7 .
a. Synthesis section
i. Set the Create HDL design files for synthesis to None to inhibit the generation of
synthesis files.
ii. Uncheck the Create block symbol file (.bsf) check box.
b. Simulation section
i. Set the Create simulation model to Verilog.