Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 402)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 402
VHDL Test Programs
AXI4-Lite VHDL Slave BFM Test Program
April 2014
type memory_t is array (0 to 2**16-1) of std_logic_vector(7 downto 0);
--///////////////////////////////////////////////
-- Code user could edit according to requirements
--///////////////////////////////////////////////
-- Variable : m_wr_addr_phase_ready_delay
signal m_wr_addr_phase_ready_delay : integer := 2;
-- Variable : m_rd_addr_phase_ready_delay
signal m_rd_addr_phase_ready_delay : integer := 2;
-- Variable : m_wr_data_phase_ready_delay
signal m_wr_data_phase_ready_delay : integer := 2;
-- Storage for a memory
shared variable mem : memory_t;
procedure do_byte_read(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : out std_logic_vector(7 downto 0));
procedure do_byte_write(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : in std_logic_vector(7 downto 0));
procedure set_wr_resp_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t);
procedure set_wr_resp_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t);
procedure set_read_data_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t);
procedure set_read_data_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t);
-- Procedure : do_byte_read
-- Procedure to provide read data byte from memory at particular input
-- address
procedure do_byte_read(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : out std_logic_vector(7 downto 0)) is
begin
data := mem(to_integer(addr));
end do_byte_read;
-- Procedure : do_byte_write
-- Procedure to write data byte to memory at particular input address
procedure do_byte_write(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : in std_logic_vector(7 downto 0)) is
begin
mem(to_integer(addr)) := data;
end do_byte_write;
-- Procedure : set_wr_resp_valid_delay
-- This is used to set write response phase valid delay to start driving
-- write response phase after specified delay.
procedure set_wr_resp_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t) is
begin
set_write_response_valid_delay(2, id, index, tr_if);
end set_wr_resp_valid_delay;
procedure set_wr_resp_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t) is