Figure 7-1. vhdl bfm internal structure – Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual
Page 138
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Mentor Verification IP AE AXI4-Lite User Guide, V10.3
138
VHDL API Overview
April 2014
Figure 7-1. VHDL BFM Internal Structure
Test Program VHDL
SystemVerilog BFM API
Configuration
Creating
Transaction
Waiting Events
Executing
Transaction
Access
Transaction
create*_transaction
1
set_config/get_config
execute_transaction/execute*_phase
2
wait_on
get*_phase
3
get_rw_transaction/get*_phase
3
get*_addr/get*_data
3
Wire level
SystemVerilog interface
Notes: 1. Refer to the
2. Refer to the
execute_transaction(), execute*_phase()
3. Refer to the
Port map
SystemVerilog to VHDL
Rx_Transaction
queue
queue
Tx_Transaction
Configuration
Maps API calls from VHDL to SystemVerilog
Translator Package
VHDL to SystemVerilog Wrapper
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