Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 91)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 91
April 2014
Chapter 5
SystemVerilog Monitor BFM
This chapter describes the SystemVerilog monitor BFM. Each BFM has an API that contains
tasks and functions to configure the BFM and to access the dynamic
Transaction Record during
the lifetime of a transaction.
Inline Monitor Connection
The connection of a monitor BFM to a test environment differs from that of a master and slave
BFM. It is wrapped in an inline monitor interface and connected inline between a master and
slave, as shown in
Figure 5-1 . It has separate master and slave ports and monitors protocol
traffic between a master and slave. The monitor itself then has access to all the facilities
provided by the monitor BFM.
Figure 5-1. Inline Monitor Connection Diagram
Monitor BFM Protocol Support
The AXI4-Lite monitor BFM supports the AMBA AXI4 protocol with restrictions described in
“
Protocol Restrictions ” on page 17.
Monitor Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following monitor
BFM API timing and events.
The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the monitor BFM does not contain any timescale,
Slave Master
Inline monitor
Master port Slave port
Monitor