Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 388)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 388
SystemVerilog Test Programs
SystemVerilog AXI4-Lite Master BFM Test Program
April 2014
bfm.execute_transaction(trans);
data_word = trans.get_data_words();
if (data_word[7:0] == 8'h04)
$display ( "@ %t, master_test_program: Read correct data (4) at
address (0)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data (4) at
address 0, but got %d", $time, data_word[7:0]);
#100
$finish();
end
// Task : handle_write_resp_ready
// This method assert/de-assert the write response channel ready signal.
// Assertion and de-assertion is done based on following variable's
value:
// m_wr_resp_phase_ready_delay
// master_ready_delay_mode
task automatic handle_write_resp_ready;
bit seen_valid_ready;
int tmp_ready_delay;
axi4_master_ready_delay_mode_e tmp_mode;
forever
begin
wait(m_wr_resp_phase_ready_delay > 0);
tmp_ready_delay = m_wr_resp_phase_ready_delay;
tmp_mode = master_ready_delay_mode;
if (tmp_mode == AXI4_VALID2READY)
begin
fork
bfm.execute_write_resp_ready(1'b0);
join_none
bfm.get_write_response_cycle;
repeat(tmp_ready_delay - 1) bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_write_resp_ready(1'b1);
seen_valid_ready = 1'b1;
end
else // AXI4_TRANS2READY
begin
if (seen_valid_ready == 1'b0)
begin
do
bfm.wait_on(AXI4_CLOCK_POSEDGE);
while (!((bfm.BVALID === 1'b1) && (bfm.BREADY === 1'b1)));
end
fork
bfm.execute_write_resp_ready(1'b0);
join_none
repeat(tmp_ready_delay) bfm.wait_on(AXI4_CLOCK_POSEDGE);