Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 23)

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AXI4-Lite Transactions
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 23
April 2014
and *READY, that indicates valid information on a channel and the acceptance of the
information from the channel.
AXI4-Lite Write Transaction Master and Slave Roles
Note
The following description of a write transaction references SystemVerilog BFM API
tasks. There are equivalent VHDL BFM API procedures that perform the same
functionality.
For a write transaction, the master calls the create_write_transaction() task to define the
information to be transferred and then calls the execute_transaction() task to initiate the transfer
of information as Figure 1-1 illustrates.
Figure 1-1. Execute Write Transaction
The execute_transaction() task results in the master calling the execute_write_addr_phase()
task followed by the execute_write_data_phase() task as illustrated in Figure 1-2 .
Master
interface Slave
interface
Write
data
Write response channel
Write data channel
Write address channel
Write
response
Address
and
control
execute_transaction(t)