Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 347)

VHDL Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 347
April 2014
variable is previously defined to hold the transaction_id. If the queue is empty, then
pop_transaction_id() will block until content is available.
The call to set_read_data_valid_delay() configures the RVALID signal delay.
In a loop, the call to the get_read_addr() helper procedure returns the actual address addr for a
particular byte location and the byte_length of the data phase (beat). This byte address is used to
read the data byte from
Internal Memory with the call to do_byte_read() , and the
set_read_data() helper procedure sets the byte in the read transaction record. If the returned
byte_length>1, then the code performs in the byte_length loop the reading and setting of the
read data from internal memory for the whole of the read data phase (beat).
The read data phase is executed over the protocol signals by calling
execute_read_data_phase() .The loop completes and restarts by waiting for another
transaction_id to be placed into the queue.
Example 11-14. handle_read
end process;-- handle_read : read data and response through path 4
-- This process reads data from memory and send read data/response
process
variable read_trans: integer;
variable byte_length : integer;
variable addr : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
loop
pop_transaction_id(read_trans, AXI4_QUEUE_ID_1, index, AXI4_PATH_4,
axi4_tr_if_4(index));
set_read_data_valid_delay(read_trans, AXI4_PATH_4,
axi4_tr_if_4(index));
get_read_addr(read_trans, 0, byte_length, addr, index, AXI4_PATH_4,
axi4_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, 0, byte_length, addr, data, index,
AXI4_PATH_4, axi4_tr_if_4(index));
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_read_addr(read_trans, j, byte_length, addr, index,
AXI4_PATH_4, axi4_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, j, byte_length, addr, data, index,
AXI4_PATH_4, axi4_tr_if_4(index));
end loop;
end if;
execute_read_data_phase(read_trans, index, AXI4_PATH_4,
axi4_tr_if_4(index));
end loop;
wait;
end process;