Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 392)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 392
SystemVerilog Test Programs
SystemVerilog AXI4-Lite Slave BFM Test Program
April 2014
///////////////////////////////////////////////////////////////////////
// Code user do not need to edit
// Please note that in this part of code base below valid delays are
assigned
// which user might need to change according to requirement
// data_valid_delay : This is for sending read data/response valid
///////////////////////////////////////////////////////////////////////
initial
begin
// Initialisation
bfm.wait_on(AXI4_RESET_0_TO_1);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
// Traffic generation
fork
process_read;
process_write;
handle_write_addr_ready;
handle_read_addr_ready;
handle_write_data_ready;
join
end
// Task : process_read
// This method keep receiving read address phase and calls another
method to
// process received transaction.
task process_read;
forever
begin
axi4_transaction read_trans;
read_trans = bfm.create_slave_transaction();
bfm.get_read_addr_phase(read_trans);
fork
begin
automatic axi4_transaction t = read_trans;
handle_read(t);
end
join_none
#0;
end
endtask
// Task : handle_read
// This method reads data from memory and send read data/response either
at
// burst or phase level depending upon slave working mode.
task automatic handle_read(input axi4_transaction read_trans);
addr_t addr[];
bit [7:0] mem_data[];
set_read_data_valid_delay(read_trans);
void'(bfm.get_read_addr(read_trans, 0,addr));
mem_data = new[addr.size()];