Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 39)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 39
April 2014
Chapter 3
SystemVerilog Master BFM
This chapter provides information about the SystemVerilog master BFM. Each BFM has an
API that contains tasks and functions to configure the BFM and to access the dynamic
Transaction Record during the lifetime of the transaction.
Master BFM Protocol Support
The AXI4-Lite master BFM supports the AMBA AXI4-Lite protocol with restrictions described
in “
Protocol Restrictions ” on page 17.
Master Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following master
BFM API timing and events.
The AMBA AXI Protocol Specification does not define any timescale or clock period with
signal events sampled and driven at rising ACLK edges. Therefore, the master BFM does not
contain any timescale, timeunit, or timeprecision declarations with the signal setup and hold
times specified in units of simulator time-steps.
The simulator time-step resolves to the smallest of all the time-precision declarations in the test
bench and design IP as a result of these directives, declarations, options, or initialization files:
•
` timescale directives in design elements
•
Timeprecision declarations in design elements
•
Compiler command-line options
•
Simulation command-line options
•
Local or site-wide simulator initialization files
If there is no timescale directive, the default time unit and time precision are tool specific. The
recommended practice is to use timeunit and timeprecision declarations. For details, refer to
Section 3.14, “System Time Units and Precision,” of the IEEE Standard for
SystemVerilog—Unified Hardware Design, Specification, and Verification Language, IEEE Std
1800
™
-2012 , February 21, 2013. This user guide refers to this document as the IEEE Standard
for SystemVerilog.