Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual

Page 382

Advertising
background image

Mentor Verification IP AE AXI4-Lite User Guide, V10.3

382

AXI4-Lite Assertions

April 2014

AXI4-
60186

AXI4_WUSER_UNKN

WUSER has an X value/WUSER has
a Z value.

AXI4-
60187

AXI4_WVALID_DEASSERTED_BEFORE_
WREADY

WVALID has been de-asserted
before WREADY was asserted.

A3.2.1

AXI4-
60188

AXI4_WVALID_HIGH_ON_FIRST_CLOCK

A master interface must begin driving
WVALID high only at a rising clock
edge after ARESETn is HIGH.

A3.1.2

AXI4-
60189

AXI4_WVALID_UNKN

WVALID has an X value/WVALID
has a Z value.

AXI4-
60190

MVC_FAILED_POSTCONDITION

A postcondition failed.

AXI4-
60191

MVC_FAILED_RECOGNITION

An item failed to be recognized.

AXI4-
60192

AXI4_TIMEOUT_WAITING_FOR_
WRITE_DATA

Timed-out waiting for a data phase in
write data burst.

A4.6

AXI4-
60193

AXI4_EXCL_RD_WHILE_EXCL_WR_IN_
PROGRESS_SAME_ID

Master starts an exclusive read burst
while exclusive write burst with same
ID tag is in progress.

A7.2.4

AXI4-
60194

AXI4_EXCL_WR_WHILE_EXCL_RD_IN_
PROGRESS_SAME_ID

Master starts an exclusive write burst
while exclusive read burst with same
ID tag is in progress.

A7.2.4

AXI4-
60195

AXI4_DEC_ERR_ILLEGAL_FOR_MAPPED_
SLAVE_ADDR

Slave receives a burst to a mapped
address but responds with DECERR
(signaled by AXI4_DECERR).

A3.4.4

AXI4-
60196

AXI4_AWVALID_HIGH_DURING_RESET

AWVALID asserted during the reset
state.

A3.1.2

AXI4-
60197

AXI4_WVALID_HIGH_DURING_RESET

WVALID asserted during the reset
state.

A3.1.2

AXI4-
60198

AXI4_BVALID_HIGH_DURING_RESET

BVALID asserted during the reset
state.

A3.1.2

AXI4-
60199

AXI4_ARVALID_HIGH_DURING_RESET

ARVALID asserted during the reset
state.

A3.1.2

AXI4-
60200

AXI4_RVALID_HIGH_DURING_RESET

RVALID asserted during the reset
state.

A3.1.2

AXI4-
60201

AXI4_ARESETn_SIGNAL_Z

Reset signal has a Z value.

AXI4-
60202

AXI4_ARESETn_SIGNAL_X

Reset signal has an X value.

AXI4-
60203

AXI4_TIMEOUT_WAITING_FOR_WRITE_
ADDR_AFTER_DATA

Timed-out waiting for a write address
phase to be coming after data.

A2.2

AXI4-
60204

AXI4_EXCLUSIVE_WRITE_BYTES_
TRANSFER_EXCEEDS_128

Number of bytes in an exclusive
write transaction must be less than
or equal to 128.

A7.2.4

Table A-1. AXI4 Assertions (cont.)

Error
Code

Error Name

Description

Property
Ref

Advertising