Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 59)

SystemVerilog Master BFM
get_write_response_cycle()
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 59
April 2014
get_write_response_cycle()
This blocking task waits until the write response channel BVALID signal is asserted.
Example
// Wait until the write response channel BVALID signal is asserted.
bfm.get_write_response_cycle();
Prototype task automatic get_write_response_cycle();
Arguments None
Returns None