Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 133)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 133
April 2014
Example 6-19. handle_read
// Task : handle_read
// This method reads data from memory and send read data/response either
at
// burst or phase level depending upon slave working mode.
task automatic handle_read(input axi4_transaction read_trans);
addr_t addr[];
bit [7:0] mem_data[];
set_read_data_valid_delay(read_trans);
void'(bfm.get_read_addr(read_trans, 0,addr));
mem_data = new[addr.size()];
for(int j = 0; j < addr.size(); j++)
mem_data[j] = do_byte_read(addr[j]);
bfm.set_read_data(read_trans, 0, addr, mem_data);
bfm.execute_read_data_phase(read_trans);
endtask
process_write()
The processing of write transactions in the slave test program works in a similar way as that
previously described for the
process_read() task.
Example 6-20. process_write
// Task : process_write
// This method keep receiving write address phase and calls another
// method to process received transaction.
task process_write;
forever
begin
axi4_transaction write_trans;
write_trans = bfm.create_slave_transaction();
bfm.get_write_addr_phase(write_trans);
fork
begin
automatic axi4_transaction t = write_trans;
handle_write(t);
end
join_none
#0;
end
endtask
handle_write()
The handle_write() task works in a similar way as that previously described for the
handle_read() task. The main difference is that the write transaction handling gets the write data
phase and stores it in the slave test program Internal Memory , and adhering to the state of the