Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 400)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 400
VHDL Test Programs
AXI4-Lite VHDL Master BFM Test Program
April 2014
wait;
end process;
-- handle_write_resp_ready : write response ready through path 5.
-- This method assert/de-assert the write response channel ready signal.
-- Assertion and de-assertion is done based on following variable's
value:
-- m_wr_resp_phase_ready_delay
process
variable tmp_ready_delay : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, AXI4_PATH_5, axi4_tr_if_5(index));
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5, axi4_tr_if_5(index));
loop
wait until m_wr_resp_phase_ready_delay > 0;
tmp_ready_delay := m_wr_resp_phase_ready_delay;
execute_write_resp_ready(0, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
get_write_response_cycle(index, AXI4_PATH_5, axi4_tr_if_5(index));
if(tmp_ready_delay > 1) then
for i in 0 to tmp_ready_delay-2 loop
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
end if;
execute_write_resp_ready(1, 1, index, AXI4_PATH_5,
axi4_tr_if_5(index));
end loop;
wait;
end process;
-- handle_read_data_ready : read data ready through path 6.
-- This method assert/de-assert the read data channel ready signal.
-- Assertion and de-assertion is done based on following variable's
value:
-- m_rd_data_phase_ready_delay
process
variable tmp_ready_delay : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, AXI4_PATH_6, axi4_tr_if_6(index));
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_6, axi4_tr_if_6(index));
loop
wait until m_rd_data_phase_ready_delay > 0;
tmp_ready_delay := m_rd_data_phase_ready_delay;
execute_read_data_ready(0, 1, index, AXI4_PATH_6,
axi4_tr_if_6(index));
get_read_data_cycle(index, AXI4_PATH_6, axi4_tr_if_6(index));
if(tmp_ready_delay > 1) then
for i in 0 to tmp_ready_delay-2 loop
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_6,
axi4_tr_if_6(index));
end loop;
end if;
execute_read_data_ready(1, 1, index, AXI4_PATH_6,
axi4_tr_if_6(index));
end loop;
wait;
end process;